1. Field of the Invention
The present invention relates to a semiconductor memory device having a sub-word line driving circuit, and in particular to a semiconductor memory device having a sub-word line driving circuit which can simplify a layout thereof and reduce a size of a memory chip by decreasing the number of additional NMOS transistors for connecting sub-word lines to a ground.
2. Description of the Background Art
In general, a semiconductor memory device includes: a decoder decoding an inputted address signal; and a sub-word line driving circuit driving a sub-word line to store a data in a specific memory cell or output the data stored in the memory cell through a bit line according to an output signal from the decoder. The semiconductor memory device having the sub-word line driving circuit will now be described in detail with reference to the accompanying drawings. Here, the semiconductor memory device including eight sub-word lines are exemplified. However, the number of the sub-word lines may be varied, if necessary.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device having a sub-word line driving circuit. As shown in FIG. 1, the semiconductor memory device includes: a row decoder 10 receiving high significant predecoding signals P4-Px obtained by predecoding externally-inputted high significant row address signals and outputting inverted first and second global word line enable signals GWLB0, GWBL1; a first sub-word line driving unit 20 selectively outputting first and second low significant predecoding signals P0, P1 obtained by predecoding externally-inputted low significant row address signals or a ground potential to corresponding sub-word lines according to the inverted first and second global word line enable signals GWLB0, GWLB1 and inverted first and second low significant predecoding signals PB0, PB1; a second sub-word line driving unit 30 selectively outputting third and fourth low significant predecoding signals P2, P3 obtained by predecoding externally-inputted low significant row address signals or the ground potential to corresponding sub-word lines according to the inverted first and second global word line enable signals GWLB0, GWLB1 and inverted third and fourth low significant predecoding signals PB2, PB3; and a memory cell array 40 having a plurality of memory cells storing a data or outputting a stored data through bit lines BL0-BL3, the specific sub-word line being enabled according to the low significant predecoding signal selectively outputted from the first and second sub-word line driving units 20, 30.
Here, the first and second sub-word line driving units 20, 30 and the memory cell array 40 are provided in a single unit, and may be employed in multiple number, if necessary.
FIG. 2 is a detailed circuit diagram illustrating the first and second sub-word line driving units 20, 30 and the memory cell array 40 which are provided in a single unit in the conventional semiconductor memory device. As illustrated in FIG. 2, the first sub-word line driving unit 20 includes first to fourth sub-word line drivers SWLD11-SWLD14 selectively respectively outputting the first to fourth low significant predecoding signals P0-P3 or the ground potential to the corresponding sub-word lines SWL0, SWL2, SWL4, SWL6 according to the inverted first and second global wordline enable signals GWLB0, GWLB1 and the inverted first to fourth low significant predecoding signals PB0-PB3.
Here, the first sub-word line driver SWLD11 includes an inverter consisting of a first PMOS transistor PM11 and a first NMOS transistor NM11-1, the inverted first global word line enable signal GWLB0 being applied to a commonly-connected gate of the first PMOS and NMOS transistors PM11, NM11-1, the first low significant predecoding signal P0 being applied to a source of the first PMOS transistor PM11, a source of the first NMOS transistor NM11-1 being connected to the ground; and a second NMOS transistor NM11-2, a first global word line enable signal GWL0 being applied to its gate, its drain being connected to the first sub-word line SWL0, its source being connected to the ground. Here, the commonly-connected drain of the first PMOS and NMOS transistors PM11, NM11-1 are connected to the first sub-word line SWL0.
The second to fourth sub-word line drivers SWLD12-SWLD14 are identically constituted to the first sub-word line driver SWLD11, and selectively output the first and second low significant predecoding signals P0, P1 or the ground voltage respectively to the third, fifth and seventh sub-word lines SWL2, SWL4, SWL6 under the control of the inverted first or second global word line enable signal GWLB0, GWLB1 and the inverted first or second low significant predecoding signal PB0, PB1.
The second sub-word line driving unit 30 is identically constituted to the first sub-word line driving unit 20. That is, the first to fourth sub-word line drivers SWLD21-SWLD24 are identically constituted to the first to fourth sub-word line drivers SWLD11-SWLD14 of the first sub-word line driving unit 20, and selectively output the third and fourth low significant predecoding signals P2, P3 or the ground voltage to the corresponding sub-word lines SWL1, SWL3, SWL5, SWL7 under the control of the inverted first and second global wordline enable signals GWLB0, GWLB1 and the inverted third and fourth low significant predecoding signals PB2, PB3.
The memory cell array 40 includes the plurality of memory cells at intersecting points of the sub-word lines SWL0-SWL7 which are respectively connected to the sub-word line drivers SWDL11-SWLD14, SWLD21-SWDL24 of the first and second sub-word line driving units 20, 30 and the bit lines BL0-BL3.
Here, the number of the sub-word line drivers is increased according to the number of the memory cells, namely an increase of the number of the sub-word lines.
The operation of the conventional semiconductor memory device having the sub-word line driving circuit will now be described.
First, when receiving the high significant predecoding signals P4-Px obtained by predecoding the high significant row address signals, the row decoder 10 decodes the signals, thereby outputting the inverted first and second global word line enable signals GWLB0, GWLB1.
The low significant predecoding signals P0-P3 obtained by predecoding the low significant address signals and the inverted signals thereof PB0-PB3 are applied to the first and second sub-word line driving units 20, 30.
Here, for example, when the inverted first global word line enable signal GLWB0 is at a low level and the first predecoding signal P0 is at a high level in the row decoder 10, the first sub-word line driver SWLD11 of the first sub-word line driving unit 20 outputs the first predecoding signal P0 of high level to the first sub-word line SWL0, thus making it possible to perform a reading/writing operation of a data by the bit lines BL0-BL3 on the memory cells of the memory cell array 40 connected to the first sub-word line SWL0.
However, the inverted second to fourth low significant predecoding signals PB1-PB3 are all at a high level, and thus the second NMOS transistors NM12-2, NM21-2, NM22-2 of the sub-word line drivers SWLD12, SWLD21, SWLD22 are turned on. As a result, the other sub-word lines SWL1-SWL7 are connected to the ground, and the data stored in the memory cells ol the memory cell array 40 connected to the corresponding sub-word lines SWL1-SWL3 are maintained.
In addition, the inverted second global word line enable signal GWLB1 is at a high level, and thus the fifth to eighth sub-word lines SWL4-SWL7 are connected to the ground by the first NMOS transistors NM13-1, NM14-1, NM23-1, NM24-1 of the sub-word line drivers SWLD13, SWLD14, SWLD23, SWLD24 connected to the sub-word lines SWL4-SWL7, regardless of the first to fourth low significant predecoding signals P0-P3. Therefore, the data stored in the memory cells of the memory cell array 40 connected to the fifth to eighth sub-word lines SWL4-SWL7 are maintained.
Identically, the sub-word lines SWL0-SWL7 may be selected and enabled by selecting and applying the inverted first and second global word line enable signals GWLB0-GWLB1 and the first to fourth low significant predecoding signals P0-P3. Thus, it makes it possible to selectively write a data on a preferable memory cell of the memory cell array 40 or read a data stored therein.
However, when the conventional semiconductor memory device is operated, the sub-word line driving units 20, 30 require the additional NMOS transistors for connecting the sub-word lines which may be floated to the ground. There are disadvantages of the conventional semiconductor memory device in that the layout thereof is complicated and a size of the memory chip is increased.